1. Field of the Invention
The present invention relates to a semiconductor memory device and a memory card, and particularly relates to a semiconductor memory device in which a modification is made to the order of supply of signals to select gate lines when data in a memory cell connected to a word line is read and a memory card equipped with such a semiconductor memory device.
2. Related Background Art
Among semiconductor memory devices, a nonvolatile semiconductor memory device which holds stored data in a nonvolatile manner is in widespread use. Some of these nonvolatile semiconductor memory devices have a memory cell array structure, for example, called a NAND type.
The NAND-type memory cell array is composed of plural NAND cell units each including plural memory cells connected in series in such a manner as to share a source/drain region, a drain-side select transistor connected on the drain side of these plural memory cells, and a source-side select transistor connected on the source side of these plural memory cells.
Further, in the memory cell array, plural word lines are provided in parallel and each connect gate electrodes of memory cells arranged in a word line direction in common. Furthermore, respective gate electrodes of drain-side select transistors arranged in the word line direction are connected in common by a drain-side select gate line, and respective gate electrodes of source-side select transistors arranged in the word line direction are connected in common by a source-side select gate line. Plural bit lines are provided in parallel in a direction crossing the word line direction, and each bit line is connected to its corresponding NAND cell unit via the drain-side select transistor.
In such a NAND-type nonvolatile semiconductor memory device, the operation when data is read from a memory cell is performed, for example, in the following manner. First, the voltage of the drain-side select gate line is increased from 0 V to approximately 4 V. Subsequently, a voltage of approximately 1 V is supplied to the bit line.
Then, a read voltage is supplied to a word line (selected word line) connected to the memory cell from which the data is to be read, and a voltage of approximately 4 V is supplied to the other word lines (non-selected word lines). Subsequently, the voltage of the source-side select gate line is increased from 0 V to approximately 4 V.
Thereafter, by detecting a potential change in the bit line, it is determined whether “0” data or “1” data is stored in the memory cell to be read. More specifically, for example, it is suitable to previously define a state in which electrons are injected into a floating gate and the threshold of the memory cell is high as the “0” data, and contrary to this, define a state in which electrons are extracted from the floating gate and the threshold of the memory cell is low as the “1” data.
The voltages are applied to the word lines, the drain-side select gate line, the source-side select gate line, and the bit line in the aforementioned timing, and as a prior application in which this timing is changed, Japanese Patent Application No. 2003-315782 exists.